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K6F8016R6D Family
Document Title
Preliminary CMOS SRAM
512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 0.1 Initial draft Revised - Updated DC parameters (ICC1, ICC2, ISB1, IDR) - Deleted 55ns Speed bin
Draft Date
April 26, 2004 September 13, 2004
Remark
Preliminary Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 0.1 September 2004
K6F8016R6D Family
FEATURES
* Process Technology: Full CMOS * Organization: 512K x16 * Power Supply Voltage: 1.65~1.95V * Low Data Retention Voltage: 1.0V(Min) * Three State Outputs * Package Type: 48-FBGA-6.00x7.00
Preliminary CMOS SRAM
GENERAL DESCRIPTION
The K6F8016R6D families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PRODUCT FAMILY
Power Dissipation Product Family K6F8016R6D-F Operating Temperature Industrial(-40~85C) Vcc Range 1.65~1.95V Speed 70ns Standby (ISB1, Typ.) 0.5A2) Operating (ICC1, Max) 2mA PKG Type 48-FBGA-6.00x7.00
1. Typical value are measured at VCC=2.0V, TA=25C and not 100% tested.
PIN DESCRIPTION
1 2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
A
LB
OE
A0
A1
A2
CS2 Vcc Vss
B
I/O9
UB
A3
A4
CS1
I/O1
Row Addresses
C
Row select
I/O10
I/O11
A5
A6
I/O2
I/O3
Memory array 1024 rows 512x16 columns
D
Vss
I/O12
A17
A7
I/O4
Vcc Data cont Data cont Data cont I/O Circuit Column select
E
Vcc
I/O13
DNU
A16
I/O5
Vss
I/O1~I/O8
F
I/O9~I/O16
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
DNU
A12
A13
WE
I/O8 Column Addresses
H
A18
A8
A9
A10
A11
DNU
CS1
48-FBGA: Top View (Ball Down)
CS2 OE WE
Control Logic
Name
Function
Name Vcc Vss UB LB DNU
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Do Not Use
UB LB
CS1, CS2 Chip Select Inputs OE WE A0~A18 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 0.1 September 2004
K6F8016R6D Family
PRODUCT LIST
Industrial Temperature Products(-40~85C) Part Name K6F8016R6D-FF70 Function 48-FBGA, 70ns, 1.8V
Preliminary CMOS SRAM
FUNCTIONAL DESCRIPTION
CS1 H X1) X
1)
CS2 X
1)
OE X
1)
WE X
1)
LB X
1)
UB X
1)
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
L X
1)
X1) X
1)
X1) X
1)
X1) H L X
1)
X1) H X
1)
L L L L L L L L
H H H H H H H H
H H L L L X1) X1) X1)
H H H H H L L L
L H L L H L L
L H L L H L
1. X means dont care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V(Max. 2.5V) -0.2 to 2.5 1.0 -65 to 150 -40 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability.
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Revision 0.1 September 2004
K6F8016R6D Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 1.65 0 1.4 -0.2
3)
Preliminary CMOS SRAM
Typ 1.8 0 Max 1.95 0 Vcc+0.2 0.4
2)
Unit V V V V
Note: 1. TA=-40 to 85C, otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current Symbol ILI ILO ICC1 ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB1 VIN=Vss to Vcc CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH IOL = 0.1mA IOH = -0.1mA Other input =0~Vcc 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0VCS20.2V(CS2 controlled) Test Conditions Min -1 -1 1.4 Typ1) 0.5 Max 1 1 2 17 0.2 10 Unit A A mA mA V V A
1. Typical values are measured at VCC=2.0V, TA=25C and not 100% tested.
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Revision 0.1 September 2004
K6F8016R6D Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V Input rising and falling time: 5ns Input and output reference voltage: 0.9V Output load(see right): CL=100pF+1TTL
Preliminary CMOS SRAM
VTM3) R12)
CL1)
R22)
1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =1.8V
AC CHARACTERISTICS(Vcc=1.65~1.95V, Industrial product: TA=-40 to 85C)
Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 70 10 10 5 0 0 0 10 70 60 0 60 60 50 0 0 30 0 5 70ns Max 70 70 35 70 25 25 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V
1) 1)
Min 1.0 0 tRC
Typ2) 0.5 -
Max 1.95 6 -
Unit V A ns
Vcc=1.2V, CS1Vcc-0.2V
See data retention waveform
1. 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0CS20.2V(CS2 controlled) 2. Typical value are measured at TA=25C and not 100% tested.
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Revision 0.1 September 2004
K6F8016R6D Family
TIMING DIAGRAMS
Preliminary CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tOH
CS1
CS2 tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 0.1 September 2004
K6F8016R6D Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tWR(4)
Preliminary CMOS SRAM
CS2 tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z
UB, LB
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 0.1 September 2004
K6F8016R6D Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS1 tAW CS2 UB, LB tBW tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
Preliminary CMOS SRAM
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 1.65V tSDR Data Retention Mode tRDR
1.4V VDR CS1VCC - 0.2V
CS1 GND
CS2 controlled
VCC 1.65V CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND CS20.2V
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Revision 0.1 September 2004
K6F8016R6D Family
PACKAGE DIMENSION
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View Bottom View B B 6 A #A1 B C D 5 4 B1
Preliminary CMOS SRAM
Unit: millimeters
3
2
1
C1 E F G H Detail A A Y E1 Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are 0.050 unless specified beside figure. 4. Typ: Typical 5. Y is coplanarity: 0.10(Max)
Side View
D E1 E C Min A B B1 C C1 D E E1 Y 5.90 6.90 0.40 0.27 Typ 0.75 6.00 3.75 7.00 5.25 0.45 Max 6.10 7.10 0.50 1.00 0.10
C
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Revision 0.1 September 2004
C

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